Research alliance builds new transistor for 5nm technology
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05-06-2017, 02:54 PM
Research alliance builds new transistor for 5nm technology

Quote:IBM, its Research Alliance partners Globalfoundries and Samsung, and equipment suppliers have developed an industry-first process to build silicon nanosheet transistors that will enable 5 nanometer (nm) chips. The details of the process will be presented at the 2017 Symposia on VLSI Technology and Circuits conference in Kyoto, Japan. In less than two years since developing a 7nm test node chip with 20 billion transistors, scientists have paved the way for 30 billion switches on a fingernail-sized chip.

The resulting increase in performance will help accelerate cognitive computing, the Internet of Things (IoT), and other data-intensive applications delivered in the cloud. The power savings could also mean that the batteries in smartphones and other mobile products could last two to three times longer than today's devices, before needing to be charged.

Scientists working as part of the IBM-led Research Alliance at the SUNY Polytechnic Institute Colleges of Nanoscale Science and Engineering's NanoTech Complex in Albany, NY achieved the breakthrough by using stacks of silicon nanosheets as the device structure of the transistor, instead of the standard FinFET architecture, which is the blueprint for the semiconductor industry up through 7nm node technology.

Definitely need more time to stare at my phone, so this is good news.
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05-06-2017, 03:57 PM (This post was last modified: 05-06-2017 04:02 PM by Deesse23.)
RE: Research alliance builds new transistor for 5nm technology
Quntum tunneling poses a major challenge to this...or major chance, depending on your view

With structures getting smaller and smaller, conventional MOSFETS will start to "leak" more and more. Since tunneling is dependent on potential differences, the leaks will be bigger with rising voltages. Ergo, conventional FETs will only keep working properly if used in low voltage circuits.

There seems to be a chance however. The otherwise adverse effect of tunneling can be used as a feature instead of plagueing your transistors as a bug (leak). Tunnel field effect transistors seem to be able to make use of this effect of quantum physics. Since FETs are a tool (in general) for circuits that need fast switching with low power, these TFETs could be able to expand on this further. Low power by using the extremely small leakage quantum tunneling provides to operate the gate (of the FET) with even lower currents than before. Being able to achieve higher drain current changes with smaller gate voltage changes to switch faster. So, TFETs could be a future application for extremely low power and / or high frequency circuits .

For comparison, conventional flash memories (which we all have) are already using the ability of electrons to tunnel across 20nm with 12V, in order to charge and discharge memory cells.

P.S.: basically flash memories are proof of quantum mechanics, just in case some nut is gonna claim to you it isnt true. In this case just point at his mobile or tablet Smile

Ceterum censeo, religionem delendam esse
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